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high p erformance, ism band, fsk/ask transceiver ic data sheet adf7020 rev. d information furnished by analog devices is believed to be accurate and reliab le. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implicati on or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 C 2012 analog devices, inc. all rights reserved. features low power, low if transceiver frequency bands 431 mhz to 478 mhz 862 mhz to 956 mhz data rates supported 0.15 kbps to 200 kbps, fsk 0.15 kbps to 64 kbps, ask 2.3 v to 3.6 v power supply programmable output power ?16 dbm to +13 dbm in 0.3 dbm step s receiver sensitivity ? 119 dbm at 1 kbps, fsk ?112 dbm at 9.6 kbps, fsk ?106.5 dbm at 9.6 kbps, ask low power consumption 19 ma in receive mode 26.8 ma in transmit mode (10 dbm output) ? 3 dbm iip3 in h igh l inearity m ode on - chip vco and fractional - n pll on - chip 7 - bit adc and temperature sensor fully automatic frequency control loop (afc) compensates for 25 ppm crystal at 862 mhz to 956 mhz or50 ppm at 431 mhz to 478 mhz digital rssi integrated t x/ rx switch leakage current of <1 a in power - down mode appli c ations low cost wireless data transfer remote control/security systems wireless metering keyless entry home automation process and building control wireless voice functional block dia gram tx/rx control agc control fsk/ask demodulator data synchronizer rssi 7-bit adc gain div r serial port rfout offset correction offset correction lna vco pfd cp afc control osc1 osc2 dividers/ muxing n/n + 1 div p mux temp sensor osc clk div clkout test mux vcoin cpout ldo(1:4) muxout adcin rset creg[1:4] r lna r fin r finb sle sdata ce data clk sread sclk int/lock data i/o fsk mod control gaussian filter - modulator 05351-001 if filter adf7020 figure 1.
adf7020 dat a sheet rev. d | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications ..................................................................................... 5 timing characteristics ..................................................................... 8 timing diagrams .......................................................................... 8 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance charact eristics ........................................... 13 frequency synthesizer ................................................................... 15 reference input ........................................................................... 15 choosing channels for best system performance ................. 17 transmitter ...................................................................................... 18 rf output stage .......................................................................... 18 modulation schemes .................................................................. 18 receiver ............................................................................................ 20 rf front end ............................................................................... 20 rss i/agc .................................................................................... 21 fsk demodulators on the adf7020 ....................................... 21 fsk correlator/demodulator ................................................... 21 linear fsk demodulator .......................................................... 23 afc .............................................................................................. 23 automatic sync word recognition ......................................... 24 applications information .............................................................. 25 lna/pa matching ...................................................................... 25 image rejection calibration ..................................................... 26 transmit protocol and coding considerations ..................... 27 device programming after initial power - up ......................... 27 interfac ing to microcontroller/dsp ........................................ 27 power consumption and battery lifetime calculations ......... 28 serial interface ................................................................................ 31 readback format ........................................................................ 31 registers ........................................................................................... 32 register 0 n register ............................................................... 32 register 1 oscillator/filter register ...................................... 33 register 2 transmit modulation register (ask/ook mode) ........................................................................................... 34 register 2 transmit modulation register (fsk mode) ..... 35 register 2 transmit modulation register (gfsk/gook mode) ........................................................................................... 36 register 3 receiver clock register ....................................... 37 register 4 demodulator setup register ............................... 38 register 5 sync byte register ................................................. 39 register 6 correlator/demodulator register ...................... 40 register 7 readback setup register ...................................... 41 regis ter 8 power - down test register .................................. 42 register 9 agc register ......................................................... 43 register 10 agc 2 register .................................................... 44 register 11 afc register ....................................................... 44 register 12 test register ......................................................... 45 register 13 offset removal and signal gain r egister ....... 46 outline dimensions ....................................................................... 47 ordering guide .......................................................................... 47
data sheet adf7020 rev. d | page 3 of 48 revision history 8 /12 rev. c to rev. d add ed epad notation ................................................................... 11 changed cp - 48- 3 pacage to cp - 48- 5 pacage .......................... 47 updated outline dimensions ........................................................ 47 changes to ordering guide ........................................................... 47 5 /11 rev. b to rev. c added exposed pad notation to outline dimensions .............. 47 changes to ordering guide ........................................................... 47 8 /07 rev. a to rev. b chan ges to features .......................................................................... 1 changes to general description ..................................................... 4 changes to table 1 ............................................................................ 5 changes to table 2 ............................................................................ 8 changes to reference input section ............................................. 15 changes to n counter section ...................................................... 16 changes to choosing channels for best performance section 17 changes to table 5 .......................................................................... 20 changes to fsk correlator register settings section ................ 22 added image reection calibration section ............................... 26 added figure 41 .............................................................................. 30 changes to readbac format section .......................................... 31 changes to register 9 agc register comments section ....... 43 added register 12 test register comments section .............. 45 4 /06 rev. 0 to rev. a changes to features .......................................................................... 1 changes to table 1 ............................................................................ 5 changes to figure 24 ...................................................................... 17 changes to the setting up the adf7020 for gfsk section ..... 19 changes to table 6 .......................................................................... 21 changes to table 9 .......................................................................... 23 changes to external afc section ................................................. 23 deleted maximum afc range secti on ....................................... 23 added afc performance section ................................................. 24 changes to internal rx/tx switch section .................................. 25 changes to figure 32 ...................................................................... 25 changes to transmit protocol and coding considerations section .............................................................................................. 26 added text relating to figure 37 ................................................. 27 changes to figure 41 ...................................................................... 31 changes to register 1 o scillator/filter register comments ........................................................................................ 31 changes to figure 42 ...................................................................... 32 changes to register 2 transmit modulation register fsk mode comments ................................................................. 33 changes to figure 44 ...................................................................... 34 changes to register 2 transmit modulation register gfsk/gook mode comments ................................................ 34 changes to re gister 4 demodulator setup register comments ........................................................................................ 36 changes to figure 51 ...................................................................... 41 changes to figure 53 ...................................................................... 42 changes to ordering guide ........................................................... 45 6/05 revision 0: initial version
adf7020 dat a sheet rev. d | page 4 of 48 general description the adf7020 is a low power, highly integrated fsk/ask/ook transceiver d esigned for operation in the license - free ism bands at 433 mhz, 868 mhz, and 915 mhz, as well as the proposed japanese rfid band at 950 mhz. a gaussian data filter option is available to allow either gfsk or g - ask modulation , which provides a more spectral ly efficient modulation. in addition to these modulation options, the adf7020 can also be used to perform both msk and gmsk modulation, where msk is a special case of fsk with a modulation index of 0.5. the modula - tion index is calculated as twice the devi ation divided by the data rate. msk is spectrally equivalent to o - qpsk modulation with half - sinusoidal tx baseband shaping, so the adf7020 can also support this modulation option by setting up the device in msk mode. this device is suitable for circuit ap plications that meet the european etsi - 300 - 220, the north american fcc (part 15) , or the chinese short range device regulatory standards. a complete transceiver can be built using a small number of external discrete components, making the adf7020 very sui table for price - sensitive and area - sensitive applications. the transmitter block on the adf7020 contains a vco and low noise fractional - n pll with an output resolution of <1 ppm. this frequency agile pll allows the adf7020 to be used in frequency - hopping spread spectrum (fhss) systems. the vco operates at twice the fundamental frequency to reduce s purious emissions and frequency - pulling problems. the transmitter output power is programmable in 0.3 db steps from ?16 dbm to +13 dbm. the transceiver rf freq uency, channel spacing, and modulation are programmable using a simple 3 - wire interface. the device operates with a power supply range of 2.3 v to 3.6 v and can be powered down when not in use. a low if architecture is used in the receiver (200 khz), minim izing power consumption and the external component count and avoiding interference problems at low frequencies. the adf7020 supports a wide variety of programmable features, including rx linearity, sensitivity, and if bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. the receiver also features a patent - pending automatic frequency control (afc) loop, allowing the pll to track out the frequency error in the incoming signa l. an on - chip adc provides readback of an integrated tempera - ture sensor, an external analog input, the battery voltage, or the rssi signal, which provides savings on an adc in some appli - cations. the temperature sensor is accurate to 10c over the full operating temperature range of ?40c to +85c. this accuracy can be improved by doing a 1 - point calibration at room temperature and storing the result in memory.
data sheet adf7020 rev. d | page 5 of 48 specifications vdd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. ty pical specifications are at vdd = 3 v, t a = 25c. all measurements are performed using the eval - adf7020db zx using the pn9 data sequence, unless otherwise noted. table 1 . parameter min tp max unit test conditions rf characteri stics frequency ranges (direct output) 862 870 mhz vco adjust = 0, vco bias = 10 902 928 mhz vco adjust = 3, vco bias = 10 928 956 mhz vco adjust = 3, vco bias = 12, vdd = 2.7 v to 3.6 v frequency ranges (divide - by - 2 mode) 431 440 mhz vco adjust = 0, vco bias = 10 440 478 mhz vco adjust = 3, vco bias = 12 phase frequency detector frequency rf/256 24 mhz transmission parameters data rate fsk/gfsk 0.15 200 kbps ook/ask 0.15 64 1 kbps ook/ask 0.3 100 kbaud using manchester encoding frequency shift keying gfsk/fsk frequency deviation 2 , 3 1 110 khz pfd = 3.625 mhz 4.88 620 khz pfd = 20 mhz deviation frequency resolution 100 hz pfd = 3.625 mhz gaussian filter bt 0.5 amplitude shift keying ask modulation depth 30 db pa off feedthrough in ook mode ?50 dbm transmit power 4 ?20 +13 dbm vdd = 3.0 v, t a = 25c transmit power variation vs. temperature 1 db from ? 40c to +85 c transmit power variation vs. vdd 1 db from 2 .3 v to 3.6 v at 915 mhz, t a = 25c transmit power flatness 1 db from 902 mhz to 928 mhz, 3 v, t a = 25c programmable step size ?20 dbm to +13 dbm 0.3125 db integer boundary ?55 dbc 50 khz loop bw reference ?65 dbc harmonics second harmonic ?27 dbc unfiltered conductive third harmonic ?21 dbc all other harmonics ?35 dbc vco frequency pulling, ook mode 30 khz rms dr = 9.6 kbps optimum pa load impedance 5 39 + j61 ? frf = 915 mhz 48 + j54 ? frf = 868 mhz 54 + j94 ? frf = 433 mhz receiver parameters fsk/gfsk input sensitivity at ber = 1e ? 3, frf = 915 mhz, lna and pa matched separately 6 sensitivity at 1 kbps ?119.2 dbm fdev = 5 khz, high sensitivity mode 7 sensitivity at 9.6 kbps ?112 .8 dbm fdev = 10 khz, high sensitivity mode sensitivity at 200 kbps ?100 dbm fdev = 50 khz, high sensitivity mode ook input sensitivity at ber = 1e ? 3, frf = 915 mhz sensitivity at 1 kbps ?116 dbm high sensitivity mode sensitivity at 9.6 kbps ?106.5 dbm high sensitivity mode
adf7020 dat a sheet rev. d | page 6 of 48 parameter min typ max unit test conditions lna and mixer, input ip3 7 enhanced linearity mode ?3 dbm pin = ?20 dbm, 2 cw interferers low current mode ?5 dbm frf = 915 mhz, f1 = frf + 3 mhz high sensitivity mode ?24 dbm f2 = frf + 6 mhz, maximum gain rx spurious emissions 8 ?57 dbm <1 ghz at antenna input ?47 dbm >1 ghz at antenna input afc pull - in range at 868 mh z/915 mhz 50 khz if_bw = 200 khz pull - in range at 433 mhz 25 khz if_bw = 20 0 khz response time 48 bits modulation index = 0.875 accuracy 1 khz channel filtering desired signal 3 db above the input sensitivity level, cw interferer power level increased until ber = 10 ?3 , image channel excluded adjacent channel reje ction (offset = 1 if filter bw setting) 27 db if filter bw settings = 100 khz, 150 khz, 200 khz second adjacent channel rejection (offset = 2 if filter bw setting) 50 db if filter bw settings = 100 khz, 150 khz, 200 khz third adjacent channel rejection (offset = 3 if filter bw setting) 55 db if filter bw settings = 100 khz, 150 khz, 200 khz image channel rejection ( uncalibrated ) 3 0 db image at frf = 400 khz image channel rejection ( calibrated ) 50 db image at frf = 400 khz co - channe l rejection ?2 db wideband interference rejection 70 db swept from 100 mhz to 2 ghz, measured as channel rejection blocking desired signal 3 db above the input sensitivity level, cw interferer power level increased until ber = 10 ?2 1 mhz 60 db 5 mhz 68 db 10 mhz 65 db 10 mhz (high linearity mode) 72 db saturation (maximum input level) 12 dbm fsk mode, ber = 10 ?3 lna input impedance 24 ? j60 ? frf = 915 mhz, rfin to gnd 26 ? j63 ? frf = 868 mhz 71 ? j128 ? frf = 4 33 mhz rssi range at input ?110 to ?24 dbm linearity 2 db absolute accuracy 3 db response time 150 s see the rssi/agc section phase - locked loop vco gain 65 mhz/v 902 mhz to 928 mhz band, vc o adjust = 0, vco_bias_setting = 10 130 mhz/v 860 mhz to 870 mhz band, vco adjust = 0 65 mhz/v 433 mhz, vco adjust = 0 phase noise (in - band) ?89 dbc/hz pa = 0 dbm, vdd = 3.0 v, pfd = 10 mhz, frf = 915 mhz, vco_bias_setting = 10 phase noise (o ut - of - band) ?110 dbc/hz 1 mhz offset residual fm 128 hz from 200 hz to 20 khz, frf = 868 mhz pll settling 40 s measured for a 10 mhz frequency step to within 5 ppm accuracy, pfd = 20 mhz, lbw = 50 khz
data sheet adf7020 rev. d | page 7 of 48 parameter min typ max unit test conditions reference input crystal reference 3.6 25 24 mhz external oscillator 3.625 24 mhz load capacitance 33 pf see crystal manufacturers specification sheet crystal start - up time 2.1 ms 11.0592 mhz crystal, using 33 pf load capacitors 1.0 ms using 16 pf load capacitors input level cmos levels see the reference input section adc parameters inl 1 lsb from 2.3 v to 3.6 v, t a = 25c dnl 1 lsb from 2.3 v to 3.6 v, t a = 25c timing information chip enabled to regulator ready 10 s c reg = 100 nf chip enabled to rssi ready 3.0 ms see table 11 for more details tx to rx turnaround time 150 s + (5 t bit ) time to synchronized data out, includes agc settling; see the agc information and timing section logic inputs input high voltage, v inh 0.7 vdd v input low voltage, v inl 0.2 vdd v input current, i inh /i inl 1 a input capacitance, c in 10 pf control clock input 50 mhz logic outputs output high volt age, v oh dvdd ? 0.4 v i oh = 500 a output low voltage, v ol 0.4 v i ol = 500 a clk out rise/fall 5 ns clk out load 10 pf temperature range, t a ?40 +85 c power supplies voltage supply vdd 2.3 3.6 v all vdd pins must be tied to gether transmit current consumption frf = 915 mhz, vdd = 3.0 v, pa is matched to 50 ? ?20 dbm 14.8 ma combined pa and lna matching network as on eval - adf7020dbzx boards vco_bias_setting = 12 ?10 dbm 15.9 ma 0 dbm 19.1 ma 10 dbm 28.5 ma 10 dbm 26.8 ma pa matched separately with external antenna switch, vco_bias_setting = 12 receive current consumption low current mode 19 ma high sensitivity mode 21 ma power - down mode low power sleep mode 0.1 1 a 1 higher data rates are achievable , depending on local regulations. 2 for the definition of frequency deviation, see the register 2 transmit modulation register (fsk mode) section. 3 for the definition of gfsk frequency deviation, see the register 2 transmit modulation register (gfsk/gook mode) section. 4 measured as maximum unmodulated power. output power varies with both supply and temperature. 5 for matching detail s, see the lna/pa matching section and the an - 764 application n ote. 6 sensitivity for combined matching network case is typically 2 db less than separate matching networks. 7 see table 5 for a description o f different receiver modes. 8 follow the matching and layout guidelines to achieve the relevant fcc/etsi specifications.
adf7020 data sheet rev. d | page 8 of 48 timing characteristics vdd = 3 v 10%, vgnd = 0 v, t a = 25c, unless otherwise noted. guaranteed by design, not production tested. table 2. parameter limit at t min to t max unit test conditions/comments t 1 >10 ns sdata to sclk setup time t 2 >10 ns sdata to sclk hold time t 3 >25 ns sclk high duration t 4 >25 ns sclk low duration t 5 >10 ns sclk to sle setup time t 6 >20 ns sle pulse width t 8 <25 ns sclk to sread data valid, readback t 9 <25 ns sread hold time after sclk, readback t 10 >10 ns sclk to sle disable time, readback timing diagrams sclk sle db31 (msb) db30 db2 db1 (control bit c2) sdata db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 t 5 05351-002 figure 2. serial interface timing diagram t 8 t 3 t 1 t 2 t 10 t 9 x rv16 rv15 rv2 rv1 05351-003 sclk sdata sle sread (control bit c1) r7_db0 figure 3. readback timing diagram
data sheet adf7020 rev. d | page 9 of 48 rxclk data rxdat a 1 data rate/32 1/data rate 05351-004 figure 4. rxdata/rxclk timing diagram txclk data txdat a sample fetch 1/data rate notes 1. txclk only available in gfsk mode. 0 5351-005 figure 5. txdata/txclk timing diagram
adf7020 dat a sheet rev. d | page 10 of 48 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating vdd to gnd 1 ? 0.3 v to +5 v analog i/o voltage t o gnd ? 0.3 v to avdd + 0.3 v digital i/o voltage to gnd ? 0.3 v to dvdd + 0.3 v operating temperature range industrial (b version) ? 40c to +85c storage temperature range ? 65c to +125c maximum junction temperature 150c mlf ja thermal impedance 2 6c/w reflow soldering peak temperature 260c time at peak temperature 40 sec 1 gnd = gnd1 = rfgnd = gnd4 = vco gnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at the se or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integ rated circuit with an esd rating of <2 kv, and is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
data sheet adf7020 rev. d | page 11 of 48 pin configuration and fu nction descriptions 0 5351-006 adf7020 top view (not to scale) vcoin creg1 vdd1 rfout rfgnd rfin rfinb r lna vdd4 rset creg4 gnd4 clkout data cl k data i/o int/lock vdd2 creg2 adcin gnd2 sclk sread sdata sle cvco gnd1 gnd vco gnd gnd vdd cpout creg3 vdd3 osc1 osc2 muxout mix_i mix_q filt_i gnd4 filt_q gnd4 test_a ce filt_q filt_i mix_q mix_i 1 2 3 4 5 6 7 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 4 4 4 5 4 6 4 7 4 8 4 3 4 2 4 1 4 0 3 9 3 8 3 7 25 26 27 28 29 30 31 32 33 34 35 36 8 9 10 11 12 notes 1. exposed pad must be connected to gro und. figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vcoin the tuning voltage on this pin deter mines the output frequency of the volt age-controlled oscillator (vco). the higher the tuning voltage, the higher the output frequency. 2 creg1 regulator voltage for pa block. a 100 nf in parallel with a 5.1 pf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 3 vdd1 voltage supply for pa block. decoupling capacitors of 0.1 f and 10 pf should be placed as close as possible to this pin. all vdd pins should be tied together. 4 rfout the modulated signal is available at this pin. o utput power levels are from ?20 dbm to +13 dbm. the output should be impedance matched to the desired load using suitable components. see the transmitter section. 5 rfgnd ground for output stage of transmit ter. all gnd pins should be tied together. 6 rfin lna input for receiver section. input matching is re quired between the antenna and the differential lna input to ensure maximum power transfer. see the lna/pa matching section. 7 rfinb complementary lna input. see the lna/pa matching section. 8 r lna external bias resistor for lna. optimum resistor is 1.1 k with 5% tolerance. 9 vdd4 voltage supply for lna/mixer block. this pin sh ould be decoupled to ground with a 10 nf capacitor. 10 rset external resistor to set charge pump current and some internal bias currents. use 3.6 k with 5% tolerance. 11 creg4 regulator voltage for lna/mixer block. a 100 nf capa citor should be placed between this pin and gnd for regulator stability and noise rejection. 12 gnd4 ground for lna/mixer block. 13 to 18 mix_i, mix_i , mix_q, mix_q , filt_i, filt_i signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 19, 22 gnd4 ground for lna/mixer block. 20, 21, 23 filt_q, filt_q , test_a signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 24 ce chip enable. bringing ce low puts the adf7020 into complete power-down. register values are lost when ce is low, and the part must be reprogrammed once ce is brought high. 25 sle load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the fourteen latches. a latch is selected using the control bits. 26 sdata serial data input. the serial data is loaded msb first with the two lsbs as the control bits. this pin is a high impedance cmos input.
adf7020 dat a sheet rev. d | page 12 of 48 pin no. mnemonic description 27 sread serial data output. this pin is used to feed readback data from the adf7020 to t he microcontroller. the sclk input is used to clock each readback bit (afc, adc readback) from the sread pin. 28 sclk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift r egister on the clk rising edge. this pin is a digital cmos input. 29 gnd2 ground for digital section. 30 adcin analog -to - digital converter input. the internal 7 - bit adc can be accessed through this pin. full scale is 0 v to 1.9 v. readback is made using the sread pin. 31 creg2 regulator voltage for digital block. a 100 nf in parallel with a 5.1 pf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 32 vdd2 voltage supply for digital block. a de coupling capacitor of 10 nf should be placed as close as possible to this pin. 33 int/lock bidirectional pin. in output mode (interrupt mode), the adf7020 asserts the int/ lock pin when it has found a match for the preamble sequence. in input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. once the threshold is locked, nrz data can be reliably received. in this mode, a demodulation lock can be asserted with minimum delay. 34 d ata i/o transmit data input/received data output. this is a digital pin, and normal cmos levels apply. 35 data clk in receive mode, the pin outputs the synchronized data clock. the positive clock edge is matched to the center of the received data. in gfsk transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. see the gaussian frequency shift keying (gfsk) section. 36 clkout a div ided - down version of the crystal reference with output driver. the digital clock output can be used to drive several other cmos inputs, such as a microcontroller clock. the output has a 50:50 mark - space ratio. 37 muxout this pin provides the lock_detec t signal, which is used to determine if the pll is locked to the correct frequency. other signals include regulator_ready, which is an indicator of the status of the serial interface regulator. 38 osc2 the reference crystal should be connected between this pin and osc1. a tcxo reference can be used by driving this pin with cmos levels and disabling the crystal oscillator. 39 osc1 the reference crystal should be connected between this pin and osc2. 40 vdd3 voltage supply for the charge pump and p ll dividers. this pin should be decoupled to ground with a 0.01 f capacitor. 41 creg3 regulator voltage for charge pump and pll dividers. a 100 nf in parallel with a 5.1 pf capacitor should be placed between this pin and ground for regulator stability a nd noise rejection. 42 cpout charge pump output. this output generates current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 43 vdd voltage supply for vco tank circuit. thi s pin should be decoupled to ground with a 0.01 f capacitor. 44 to 47 gnd, gnd1, vco gnd grounds for vco block. 48 cvco a 22 nf capacitor should be placed between this pin and creg1 to reduce vco noise. ep exposed pad. the exposed pad must be conn ected to ground.
data sheet adf7020 rev. d | page 13 of 48 typical performance characteristics 05351-007 10mhz 10.0000khz ?87.80dbc/hz carrier power ?0.28dbm atten 0.00db mkr1 ref ?70.00dbc/hz 10.00 db/div 1khz frequency offset 1 figure 7 . phase noise response at 868.3 mhz, vdd = 3.0 v, icp = 1.5 ma 05351-008 frequency (mhz) 913.38 913.28 913.30 913.32 913.36 signal level (dbm) 10 20 30 40 50 60 70 prbs pn9 dr = 7.1kbps fdev = 4.88khz rbw = 300khz fsk gfsk figure 8 . output spectrum in fsk and gfsk modulation 05351-009 if freq (khz) 600 ?400 ?300 ?200 ?100 0 100 200 300 400 500 550 ?350 ?250 ?150 ?50 50 150 250 350 450 attenuation level (db) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 200khz filter bw 150khz filter bw 100khz filter bw figure 9 . if filter response 05351-010 stop 10.000ghz sweep 16.52ms (601pts) mkr4 3.482ghz sweep 16.52ms (601pts) start 100mhz res bw 3mhz ref 10dbm peak log 10db/div vbw 3mhz atten 20db 1 3 4 ref level 10.00dbm figure 10 . harmonic response, rf out matched to 50 ?, no filter 05351-011 stop 5.000ghz sweep 5.627s (601pts) mkr1 1.834ghz ?62.57db start 800mhz #res bw 30khz ref 15dbm atten 30db vbw 30khz norm log 10db/div lgav w1 s2 s3 fc aa (f): ftun swp 1r 1 marker 1.834000000ghz ?62.57db figure 11 . harmonic response, murata dielectric filter 05351-012 frequency (mhz) 900.80 899.60 900.00 899.80 900.20 900.40 900.60 signal level (dbm) 10 0 ?10 ?20 ?30 ?40 ?50 ook gook ask figure 12 . output spectrum in ask, ook, and gook modes, dr = 10 kbps
adf7020 dat a sheet rev. d | page 14 of 48 05351-013 pa setting 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 pa output power 20 10 15 0 5 ?10 ?5 ?20 ?15 ?25 11 a 9a 5a 7a figure 13 . pa output power vs. setting 05351-014 frequency of interferer (mhz) 1100 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 level of rejection (db) 80 70 60 50 40 30 20 10 0 ?10 figure 14 . wideband interference rejection; wanted signal (880 mhz) at 3 db above sensitivity point interferer = fm jammer (9.76 kbps, 10 khz deviation) 05351-015 20 ?120 ?100 ?80 ?60 ?40 ?20 0 20 ?20 ?60 0 ?40 ?80 ?100 ?120 actual input level rssi readback level rf input (db) rssi level (db) figure 15 . digital rssi readback linearity 05351-016 rf input level (dbm) ?114 ?113 ?112 ?111 ?110 ?109 ?108 ?107 ?106 ?124 ?123 ?122 ?121 ?120 ?119 ?118 ?117 ?116 ?115 0 ?1 ?2 ?3 ?5 ?4 ?6 ?7 ?8 3.6v, ?40c 2.4 v , +85c 3.0v, +25c data rate = 1kbps fsk if bw = 100khz demod bw = 0.77khz ber figure 16 . ber vs. vdd and temperature 05351-017 rf input level (dbm) ?90 ?122 ?121 ?120 ?119 ?118 ?117 ?116 ?115 ?114 ?113 ?112 ?111 ?110 ?109 ?108 ?107 ?106 ?105 ?104 ?103 ?102 ?101 ?100 ?99 ?98 ?97 ?96 ?95 ?94 ?93 ?92 ?91 ber 0 ?1 ?2 ?4 ?5 ?3 ?6 ?7 ?8 9.760k data rate 200.8k data rate 1.002k data rate figure 17 . ber vs. data rate (com bined matching network) separate lna and pa matching paths typically improve performance by 2 db 05351-018 frequency error (khz) 110 ?110 ?90 ?70 ?50 ?30 ?10 10 30 50 70 90 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 sensitivity (dbm) ?60 ?70 ?75 ?65 ?80 ?85 ?90 ?95 ?100 ?105 ?110 linear afc off linear afc on correlator afc off correlator afc on figure 18 . sensitivity vs. frequency error with afc on/off
data sheet adf7020 rev. d | page 15 of 48 frequency synthesize r reference input the on - board crystal oscill ator circuitry (see figure 19 ) can use an inexpensive quartz crystal as the pll reference. the oscil la - tor circuit is enabled by setting r1_db12 high. it is enabled by default on power - up and is disabled by bringing ce low. errors in the crystal can be corrected using the automatic frequency control (see the afc section) feature or by adjusting the fractional - n value (see the n counter section). a single - ended reference (tcxo, cxo) can also be used. the cmos levels should be applied to osc2 with r1_db12 set low. osc1 cp1 cp2 osc2 05351-019 figure 19 . oscillator circuit on the adf7020 two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. they should be chosen so that the series value of capacitance added to the pcb track capacitance adds up to the load capacitance of the crystal, usually 20 pf. pcb track capacitance values might vary from 2 pf to 5 pf, depending on board layout. thus , cp1 and cp2 can be calculated using: pcb l c cp2 cp c + + = 1 1 1 1 where possible, choose capacitors that have a low temperature coefficient to ensure stable frequency operation over all conditions. clkout divider and buff er the clkout circuit takes the reference clock signal from the oscillator section, shown in figure 19 , and supplies a divided - down 50:50 mark - space signal to the clkout pin. an even divide from 2 to 30 is available. this divide nu mber is set in r1_db[8:11]. on power - up, the clkout defaults to divide - by - 8. dv dd clkout enable bit clkout osc1 divider 1 to 15 05351-020 2 figure 20 . clkout stage to disable clkout, set the divide number to 0. the output buffer can drive up to a 20 pf load with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a small series resistor (50 ?) can be used to slow the clock edges to reduce these spurs at f clk . r counter the 3 - bit r counter divides the reference input frequency by an integer ranging from 1 to 7. the divided - down signal is presented as the reference clock to the phase frequency detector (pfd). the divide ratio is set in register 1. maximizing the pfd frequency reduces the n value. every doubling of the pfd give s a 3 db benefit in phas e noise , as well as reducing occurrences of spurious components. the r register defaults to r = 1 on power - up . pfd [hz] = xtal/r muxout and lock detect the muxout pin allows the user to access various digital points in the adf7020. the state of muxout is c ontrolled by bits r0_db[29:31]. regulator ready regulator ready is the default setting on muxout after the transceiver has been powered up. the power - up time of the regulator is typically 50 s. because the serial interface is powered from the regulator, t he regulator must be at its nominal voltage before the adf7020 can be programmed. the status of the regulator can be monitored at muxout. when the regulator ready signal on muxout is high, programming of the adf7020 can begin. regulator ready digital lock detect analog lock detect r counter output n counter output pll test modes ?7(6702'(6 mux control dgnd dv dd muxout 05351-021 figure 21 . muxout circuit digital lock detect digital lock detect is active high. the lock detect circuit is located at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until 25 ns phase error is detected at the pfd. because no external components are needed for digital lock detect, it is more widely used than analog lock detect. a nalog lock detect this n - channel open - drain lock detect should be operated with an external pull - up res istor of 10 k? nominal. when a lock has been detected, this output is high with narrow low going pulses.
adf7020 data sheet rev. d | page 16 of 48 voltage regulators the adf7020 contains four regulators to supply stable voltages to the part. the nominal regulator voltage is 2.3 v. each regulator should have a 100 nf capacitor connected between cregx and gnd. when ce is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 ma. bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 a, and erases all values held in the registers. the serial interface operates off a regulator supply; therefore, to write to the part, the user must have ce high and the regulator voltage must be stabilized. regulator status (creg4) can be monitored using the regulator ready signal from muxout. loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 22. 05351-022 charge pump out vco figure 22. typical loop filter configuration in fsk, the loop should be designed so that the loop bandwidth (lbw) is approximately one and a half times the data rate. widening the lbw excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. for ask systems, a wider lbw is recommended. the sudden large transition between two power levels can result in vco pulling and can cause a wider output spectrum than is desired. by widening the lbw to more than 10 times the data rate, the amount of vco pulling is reduced, because the loop settles quickly back to the correct frequency. the wider lbw can restrict the output power and data rate of ask-based systems compared with fsk-based systems. narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. careful design of the loop filter is critical to obtaining accurate fsk/gfsk modulation. for gfsk, it is recommended that an lbw of 1.0 to 1.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. the free design tool adi srd design studio? can be used to design loop filters for the adf7020. it can also be used to view the effect of loop filter bandwidth on the spectrum of the transmitted signal for different combinations of modulation type, data rates, and modulation indices. n counter the feedback divider in the adf7020 pll consists of an 8-bit integer counter and a 15-bit - fractional-n divider. the integer counter is the standard pulse-swallow type common in plls. this sets the minimum integer divide value to 31. the fractional divide value gives very fine resolution at the output, where the output frequency of the pll is calculated as ? ? ? ? ? ? ? ?? 15 2 _ _ n fractional ninteger pfdf out 05351-023 vco 4n third-order - ? modulator pfd/ charge pump 4r integer-n fractional-n reference in figure 23. fractional-n pll the maximum n divide value is the combination of the integer_n (maximum = 255) and the fractional_n (maximum = 32767/32768) and puts a lower limit on the minimum usable pfd. pfd min [hz] = maximum required output frequency /(255 + 1) for example, when operating in the european 868 mhz to 870 mhz band, pfd min equals 3.4 mhz. in the majority of cases, it is advisable to use as high a value of pfd as possible to obtain best phase noise performance. voltage controlled oscillator (vco) to minimize spurious emissions, the on-chip vco operates from 1724 mhz to 1912 mhz. the vco signal is then divided by 2 to give the required frequency for the transmitter and the required lo frequency for the receiver. the vco should be recentered, depending on the required frequency of operation, by programming the vco adjust bits r1_db[20:21]. the vco is enabled as part of the pll by the pll enable bit, r0_db28. a further frequency divide-by-2 block is included to allow operation in the lower 433 mhz and 460 mhz bands. to enable operation in these bands, r1_db13 should be set to 1. the vco needs an external 22 nf between the vco and the regulator to reduce internal noise.
data sheet adf7020 rev. d | page 17 of 48 vco bias current vco bias current can be adjusted using bit r1_db19 to bit r1_db16. to ensure vco oscillation, the minimum bias current setting under all conditions is 0xa. vco loop filter mux vco select bit to pa vco bias r1_db[16:19] 220f 05351-024 cvco pin 2 2 to n divider figure 24 . voltage - controlled oscillator (vco) choosing channels fo r best system performance the fractional - n pll allows the selection of any channel within 868 mhz to 956 mhz (and 433 mhz using divide - by - 2) to a resolution of <3 00 hz. this also facilitates frequency - hopping systems. careful selection of the xtal frequency is important to achieve best spurious and blocking performance. the architec ture of fractional - n causes some level of the nearest integer channel to couple di rectly to the rf output. this phenomenon is often referred to as integer boundary spurious. if the desired rf channel and the nearest integer channel are separated by a frequency of less than the pll loop bandwidth (lbw) , the integer boundary spurs are no t attenuated by the loop. integer boundary spurs can be significantly reduced in ampli - tude by choosing xtal values that place the wanted rf channel away from integer multiples of the pfd.
adf7020 data sheet rev. d | page 18 of 48 transmitter rf output stage the pa of the adf7020 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dbm into a 50 load at a maximum frequency of 956 mhz. the pa output current and, consequently, the output power are programmable over a wide range. the pa configurations in fsk/gfsk and ask/ook modulation modes are shown in figure 25 and figure 26, respectively. in fsk/gfsk modulation mode, the output power is independent of the state of the data i/o pin. in ask/ook modulation mode, it is dependent on the state of the data i/o pin and bit r2_db29, which selects the polarity of the txdata input. for each transmission mode, the output power can be adjusted as follows: ? fsk/gfsk the output power is set using bits r2_db[9:14]. ? ask the output power for the inactive state of the txdata input is set by bits r2_db[15:20]. the output power for the active state of the txdata input is set by bits r2_db[9:14]. ? ook the output power for the active state of the txdata input is set by bits r2_db[9:14]. the pa is muted when the txdata input is inactive. idac 2 6 r2_db[9:14] r2_db4 r2_db5 digital lock detect r2_db[30:31] + rfgnd rfout from vco 05351-025 figure 25. pa configuration in fsk/gfsk mode idac r2_db[9:14] r2_db[15:23] r2_db4 r2_db5 digital lock detect r2_db[30:31] r2_db29 + rfgnd rfout from vco 05351-026 6 6 6 0 ask/ook mode data i/o figure 26. pa configuration in ask/ook mode the pa is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. depending on the applica- tion, one can design a matching network for the pa to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or mono- pole antennas. see the lna/pa matching section for details. pa bias currents control bits r2_db[30:31] facilitate an adjustment of the pa bias current to further extend the output power control range, if necessary. if this feature is not required, the default value of 7 a is recommended. the output stage is powered down by resetting bit r2_db4. to reduce the level of undesired spurious emissions, the pa can be muted during the pll lock phase by toggling this bit. modulation schemes frequency shift keying (fsk) frequency shift keying is implemented by setting the n value for the center frequency and then toggling this with the txdata line. the deviation from the center frequency is set using bits r2_db[15:23]. the deviation from the center frequency in hz is 14 2 ]hz[ number modulation pfd fsk deviation ? ? where modulation number is a number from 1 to 511 (r2_db[15:23]). select fsk using bits r2_db[6:8]. 05351-027 vco n third-order - ? modulator pfd/ charge pump 4r integer-n fractional-n pa stage ? f dev + f dev txdata fsk deviation frequency figure 27. fsk implementation
data sheet adf7020 rev. d | page 19 of 48 gaussian frequency sh ift keying (gfsk) gaussian frequency shift keying reduces the bandwidth occu - pied by the transmitted spectrum by digitally prefiltering the txdata. a txclk output line is provided from the adf7020 for synchroni zation of txdata from the micro controller. th e txclk line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate. setting up the adf7020 for gfsk to set up the frequency deviation, set the pfd and the modula - tion control bits . 12 2 2 ] hz [ m deviation pfd gfsk = where m is gf sk_mod _c ontrol , set using r2_db[24:26]. to set up the gfsk data rate , counter index factor divider pfd dr _ _ ] bps [ = the index_counter variable controls the number of inter - mediate frequency steps between the low and high frequency. it is usually p ossibl e to achieve a given data rate with various combinations of divider_factor and index_counter. choosing a higher index_counter can help in improving the spectral performance. amplitude shift keying (ask) amplitude shift keying is implemented by switching t he output stage between two discrete power levels. this is accomplished by toggling the dac, which controls the output level between two 6 - bit values set up in register 2. a 0 txdata bit sends bits r2_db[15:20] to the dac. a high txdata bit sends bits r2 _db[9:14] to the dac. a maximum modulation depth of 30 db is possible. on - off keying (ook) on - off keying is implemented by switching the output stage to a certain power level for a high txdata bit and switching the output stage off for a zero. for ook, th e transmitted power for a high input is programmed using bits r2_db[9:14]. gaussian on - off keying (gook) gaussian on - off keying represents a prefiltered form of ook modulation. the usually sharp symbol transitions are replaced with smooth gaussian filtere d transitions, the result being a reduction in frequency pulling of the vco. frequency pulling of the vco in ook mode can lead to a wider than desired bw, especially if it is not possible to increase the loop filter bw > 300 khz. the gook sampling clock samples data at the data rate (see the setting up the adf7020 for gfsk section).
adf7020 data sheet rev. d | page 20 of 48 receiver rf front end the adf7020 is based on a fully integrated, low if receiver architecture. the low if architecture facilitates a very low external component count and does not suffer from power line- induced interference problems. figure 28 shows the structure of the receiver front end. the many programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suitable for their applications. to achieve a high level of resilience against spurious reception, the lna features a differential input. switch sw2 shorts the lna input when transmit mode is selected (r0_db27 = 0). this feature facili- tates the design of a combined lna/pa matching network, avoiding the need for an external rx/tx switch. see the lna/pa matching section for details on the design of the matching network. 05351-028 sw2 lna rfin rfinb t x/rx select (r0_db27) lna mode (r6_db15) lna current (r6_db[16:17]) mixer linearity (r6_db18) lo i (to filter) q (to filter) lna gain (r9_db[20:21]) lna/mixer enable (r8_db6) figure 28. adf7020 rf front end the lna is followed by a quadrature down conversion mixer, that converts the rf signal to the if frequency of 200 khz. it is important to consider that the output frequency of the synthesizer must be programmed to a value 200 khz below the center frequency of the received channel. the lna has two basic operating modes: high gain/low noise mode and low gain/low power mode. to switch between these two modes, use the lna_mode bit, r6_db15. the mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, r6_db18. based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits lna_mode (r6_db15) and mixer_linearity (r6_db18), as outlined in table 5. the gain of the lna is configured by the lna_gain field, r9_db[20:21], and can be set by either the user or the automatic gain control (agc) logic. if filter settings/calibration out-of-band interference is rejected by means of a fourth-order butterworth polyphase if filter centered around a frequency of 200 khz. the bandwidth of the if filter can be programmed between 100 khz and 200 khz by using control bits r1_db[22:23] and should be chosen as a compromise between interference rejec- tion, attenuation of the desired signal, and the afc pull-in range. to compensate for manufacturing tolerances, the if filter should be calibrated once after power-up. the if filter calibra- tion logic requires that the if filter divider in bits r6_db[20:28] be set as dependent on the crystal frequency. once initiated by setting bit r6_db19, the calibration is performed automatically without any user intervention. the calibration time is 200 s, during which the adf7020 should not be accessed. it is important not to initiate the calibration cycle before the crystal oscillator has fully settled. if the agc loop is disabled, the gain of if filter can be set to three levels using the filter_gain field, r9_db[20:21]. the filter gain is adjusted automatically, if the agc loop is enabled. table 5. lna/mixer modes receiver mode lna mode (r6_db15) lna gain value (r9_db[20:21]) mixer linearity (r6_db18) sensitivity (dr = 9.6 kbps, f dev = 10 khz) rx current consumption (ma) input ip3 (dbm) high sensitivity mode (default) 0 30 0 ?110.5 21 ?24 rxmode2 1 10 0 ?104 20 ?13.5 low current mode 1 3 0 ?94 19 ?5 enhanced linearity mode 1 3 1 ?88 19 ?3 rxmode5 1 10 1 ?98 20 ?10 rxmode6 0 30 1 ?107 21 ?20
data sheet adf7020 rev. d | page 21 of 48 rssi/agc the rssi is implemented as a successive compres sion log amp following the base band channel filtering. the log amp achieves 3 db log linearity. it also doubles as a limiter to convert the signal - to - digital levels for the fsk demodulato r. the rssi itself is used for amplitude shift keying (ask) demodulation. in ask mode, extra digital filtering is performed on the rssi value. offset correction is achieved using a switched capacitor integra - tor in feedback around the log amp. this uses th e baseband offset clock divide. the rssi level is converted for user readback and digitally controlled agc by an 80 - level (7 - bit) flash adc. this level can be converted to input power in dbm. 1 fwr notes 1. fwr = full wave rectifier fwr fwr fwr latch a a a r clk adc offset correction rssi ask demod fsk demod 05351-029 figure 29 . rssi block diagram rssi th resholds when the rssi is above agc_high_threshold, the gain is reduced. when the rssi is below agc_low_threshold, the gain is increased. a delay (agc_delay) is programmed to allow for settling of the loop. the user programs the two threshold values (reco mmended defaults of 30 and 70) and the delay (default of 10). the default agc setup values should be adequate for most applications. the threshold values must be chosen to be more than 30 apart for the agc to operate correctly. offset correction clock in r egister 3, the user should set the bb offset clock divide bits r3_db[4:5] to give an offset clock between 1 mhz and 2 mhz. bbos_clk (hz) = xtal /( bbos_clk_divide ) where bbos_clk_divide can be set to 4, 8, or 16. agc information and timing agc is selected by default, and operates by selecting the appropri - ate lna and filter gain settings for the measured rssi level. it is possible to disable agc by writing to register 9 if enter ing one of the modes listed in table 5 is desired , for example. the time for the agc circuit to settle and, therefore , the time to take an accurate rssi measurement is typically 150 s, although this depends on how many gain settings the agc circuit has to cycle through. after each gain change, the agc loop w aits for a programmed time to allow transients to settle. this wait time can be adjusted to speed up this settling by adjusting the appropriate parameters. xtal clk seq delay agc time wait agc _ _ _ _ = agc settling = agc_wait_time number of gain changes thus, in the worst case, if the agc loop has to go through all 5 gain changes, agc_d elay =10, seq_clk = 200 khz, agc s ettling = 10 5 s 5 = 250 s. minimum agc_wait_time needs to be at least 25 s. rssi formula (converting to dbm) inputpower [dbm] = ?120 dbm + ( readback _ code + gain_mode_correction ) 0.5 where: readback_code is given by bit rv7 to bit rv1 in the readback register (see the readback format section). gain_mode_correction is given by the values in table 6 . lna gain and filter gain (lg2/lg1, fg2/fg1) are also obtained from the readback register. table 6 . gain mode correction lna gain (lg2, lg1) filter gain (fg2, fg1) gain mode correction h (1,1) h (1,0) 0 m (1,0) h (1,0) 24 m (1, 0) m (0,1) 45 m (1,0) l (0,0) 63 l ( 0,1 ) l (0,0) 90 el (0,0) l (0,0) 105 an additional factor should be introduce d to account for losses in the front - end matching network/antenna. fsk demodulators on the adf7020 the two fsk demodulators on the adf7020 are ? fsk correlator/demodulator ? linear demodulator select these using the demodulator select bits, r4_db[4:5]. fsk correlator/demod ulator the quadrature outputs of the if filter are first limited and then fed to a pair of digital frequency correlators that perform band - pass filtering of the binary fsk frequencies at (if + f dev ) and (if ? f dev ). data is recovered by comparing the output levels from each of the two correlators. the performance of this fre - quency discriminator approximates that of a matched f ilter detector, which is known to provide optimum detection in the presence of additive white gaussian noise ( awgn ) .
adf7020 data sheet rev. d | page 22 of 48 post demod filter data synchronizer if ? f dev if + f dev i if q limiters 0 r6_db[4:13] r3_db[8:15] r6_db[14] rxdata rxclk slice r frequency correlato r 05351-030 figure 30. fsk correlator/demodulator block diagram postdemodulator filter a second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. the bandwidth of this postdemodulator filter is programmable and must be optimized for the users data rate. if the bandwidth is set too narrow, performance is degraded due to intersymbol interference (isi). if the bandwidth is set too wide, excess noise degrades the receivers performance. typically, the 3 db bandwidth of this filter is set at approximately 0.75 times the users data rate, using bits r4_db[6:15]. bit slicer the received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. in the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on 0. therefore, the slicer threshold level can be fixed at 0, and the demodulator perform- ance is independent of the run-length constraints of the transmit data bit stream. this results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional fsk demodulators. frequency errors are removed by an internal afc loop that measures the average if frequency at the limiter output and applies a frequency correction value to the fractional-n synthesizer. this loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation (see the afc section). data synchronizer an oversampled digital pll is used to resynchronize the received bit stream to a local clock. the oversampled clock rate of the pll (cdr_clk) must be set at 32 times the data rate. see the register 3receiver clock register comments section for a definition of how to program. the clock recovery pll can accommodate frequency errors of up to 2%. fsk correlator register settings to enable the fsk correlator/demodulator, bits r4_db[5:4] should be set to 01. to achieve best performance, the bandwidth of the fsk correlator must be optimized for the specific deviation frequency that is used by the fsk transmitter. the discriminator bw is controlled in register 6 by bit r6_db[4:13] and is defined as 3 10800 _ _ ? ? ? kclk demod bwtor discrimina where: demod_clk is as defined in the register 3receiver clock register section, second comment. k = round(200 10 3 /fsk deviation) to optimize the coefficients of the fsk correlator, two addi- tional bits, r6_db14 and r6_db29, must be assigned. the value of these bits depends on whether k (as defined above) is odd or even. these bits are assigned according to table 7 and table 8. table 7. when k is even k k/2 r6_db14 r6_db29 even even 0 0 even odd 0 1 table 8. when k is odd k (k + 1)/2 r6_db14 r6_db29 odd even 1 0 odd odd 1 1 postdemodulator bandwidth register settings the 3 db bandwidth of the postdemodulator filter is controlled by bits r4_db[6:15] and is given by postdemod_bw_setting clk demod f cutoff _ 22 10 ?? ? where f cutoff i s the target 3 db bandwidth in hz of the post- demodulator filter. this should typically be set to 0.75 times the data rate (dr). some sample settings for the fsk correlator/demodulator are demod_clk = 5 mhz dr = 9.6 kbps f dev = 20 khz therefore, f cutoff = 0.75 9.6 10 3 hz postdemod_bw_setting = 2 11 7.2 10 3 hz/(5 mhz) postdemod_bw_setting = round (9.26) = 9 and k = round (200 khz)/20 khz) = 10 discriminator_bw = (5 mhz 10)/(800 10 3 ) = 62.5 = 63 (rounded to the nearest integer)
data sheet adf7020 rev. d | page 23 of 48 table 9. register settings 1 setting name register address value postdemod_bw_setting r4_db[6:15] 0x09 discriminator_bw r6_db[4:13] 0x3f dot_product r6_db14 0 rxdata_invert r6_db29 1 1 the latest version of the adf7020 configuration soft ware can aid in calculating register settings. linear fsk demodulator figure 31 shows a block diagram of the linear fsk demodulator. averaging filter envelope detector slicer frequency if level i q limite r 7 mux 1 adc rssi output linear discriminator r4_db[6:15] frequency readback and afc loop rxdata 05351-031 figure 31. block diagram of frequency measurement system and ask/ook/linear fsk demodulator this method of frequency demodulation is useful when very short preamble length is required, and the system protocol cannot support the overhead of the settling time of the internal feedback afc loop settling. a digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. the discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. the demodu- lated fsk data is recovered by threshold-detecting the output of the averaging filter, (see figure 31). in this mode, the slicer output shown in figure 31 is routed to the data synchronizer pll for clock synchronization. to enable the linear fsk demodulator, set bits r4_db[4:5] to 00. the 3 db bandwidth of the postdemodulation filter is set in the same way as the fsk correlator/demodulator, which is set in r4_db[6:15] and is defined as clk demod f setting bw postdemod cutoff _ 22 __ 10 ??? ? where f cutoff is the target 3 db bandwidth in hz of the postdemodulator filter. demod_clk is as defined in the register 3receiver clock register section, second comment. ask/ook operation ask/ook demodulation is activated by setting bits r4_db[4:5] to 10. digital filtering and envelope detecting the digitized rssi input via mux 1, as shown in figure 31, performs ask/ook demodulation. the bandwidth of the digital filter must be optimized to remove any excess noise without causing isi in the received ask/ook signal. the 3 db bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by r4 _db[6:15] as clk demod f setting bw postdemod cutoff _ 22 __ 10 ??? ? where f cutoff is the target 3 db bandwidth in hz of the postdemodulator filter. it is also recommended to adjust the peak response factor to 6 in register 10 for robust operation over the full input range. this improves the receivers am immunity performance. afc the adf7020 supports a real-time afc loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. this uses the frequency discriminator block, as described in the linear fsk demodulator section (see figure 31). the discriminator output is filtered and averaged to remove the fsk frequency modulation, using a combined averaging filter and envelope detector. in fsk mode, the output of the envelope detector provides an estimate of the average if frequency. two methods of afc, external and internal, are supported on the adf7020 (in fsk mode only). external afc the user reads back the frequency information through the adf7020 serial port and applies a frequency correction value to the fractional-n synthesizers n divider. the frequency information is obtained by reading the 16-bit signed afc_readback, as described in the readback format section, and applying the following formula: freq_rb [hz] = ( afc_readback demod_clk )/2 15 note that while the afc_readback value is a signed number, under normal operating conditions, it is positive. the frequency error can be calculated from freq_error [hz] = freq_rb (hz) ? 200 khz thus, in the absence of frequency errors, the freq_rb value is equal to the if frequency of 200 khz.
adf7020 dat a sheet rev. d | page 24 of 48 internal afc the adf7020 supports a real - time internal automatic frequency control loop. in this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer n div ider using an internal pi control loop. the internal afc control loop parameters are controlled in register 11. the internal afc loop is activated by setting r11_db20 to 1. a scaling coefficient must also be entered, based on the crystal frequency in use. this is set up in bits r11_db[4:19] and should be calculated using afc_scaling_coefficient = (500 2 24 )/ xtal therefore, using a 10 mhz xtal yields an afc scaling coefficient of 839. afc performance the improved sensitivity performance of the rx when afc is enabled and in the presence of frequency errors is shown in figure 18 . the maximum afc frequency range is 50 khz, which corresponds to 58 ppm at 868 mhz. this is the total error tolerance allowed in the link. for example, in a point - to - point system, afc can compensate for two 29 ppm crystals or one 50 ppm crystal and one 8 ppm tcxo. afc settling typically takes 48 bits to settle within 1 khz. this can be improved by increasing the postdemodulator bandwidth in register 4 a t the expense of rx sensitivity. when afc errors have been removed using either the internal or external afc, further improvement in the receivers sensi - tivity can be obtained by reducing the if filter bandwidth using bits r1_db[22:23]. automatic sync wo rd recognition the adf7020 also supports automatic detection of the sync or id fields. to activate this mode, the sync (or id) word must be preprogrammed into the adf7020. in receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin int/lock is asserted by the adf7020. this feature can be used to alert the microprocessor that a valid channel has been detected. it relaxes the computational require - ments of the microprocessor and redu ces the overall power consumption. the int/lock is automatically deasserted again after nine data clock cycles. the automatic sync/id word detection feature is enabled by selecting demodulator mode 2 or demodulator mode 3 in the demodulator setup register . do this by setting bits r4_db[25:23] = 010 or 011. bits r5_db[4:5] are used to set the length of the sync/id word, which can be 12, 16, 20, or 24 bits long. the transmitter must transmit the msb of the sync byte first and the lsb last to ensure proper al ignment in the receiver sync byte detection hardware. for systems using forward error correction ( fec ) , an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. the error tolerance valu e is assigned in bits r5_db[6:7].
data sheet adf7020 rev. d | page 25 of 48 applications information lna/pa matching the adf7020 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its rf input and output ports are properly matched to the antenna impedance. for cost-sensitive applications, the adf7020 is equipped with an internal rx/tx switch that facilitates the use of a simple combined passive pa/lna matching network. alternatively, an external rx/tx switch, such as the analog devices adg919 , can be used. it yields a slightly improved receiver sensitivity and lower transmitter power consumption. external rx/tx switch figure 32 shows a configuration using an external rx/tx switch. this configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is, therefore, more flexible and less difficult to design than the configuration using the internal rx/tx switch. the pa is biased through inductor l1, while c1 blocks dc current. both elements, l1 and c1, also form the matching network, which transforms the source impedance into the optimum pa load impedance, z opt _pa. 05351-032 pa lna pa_out rfin rfinb v bat l1 adf7020 adg919 optional bpf (saw) optional lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin antenna rx/tx ? select figure 32. adf7020 with external rx/tx switch z opt _pa depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. selecting an appropriate z opt _pa helps to minimize the tx current consumption in the application. application note an-767 contains a number of z opt _pa values for representative conditions. under certain conditions, however, it is recommended that a suitable z opt _pa value be obtained by means of a load-pull measurement. due to the differential lna input, the lna matching network must be designed to provide both a single-ended-to-differential conversion and a complex conjugate impedance match. the network with the lowest component count that can satisfy these requirements is the configuration shown in figure 32, which consists of two capacitors and one inductor. a first-order implementation of the matching network can be obtained by understanding the arrangement as two l type matching networks in a back-to-back configuration. due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the lna input must be established. the use of appropriate cad software is strongly recommended for this optimization. depending on the antenna configuration, the user may need a harmonic filter at the pa output to satisfy the spurious emission requirement of the applicable government regulations. the harmonic filter can be implemented in various ways, such as a discrete lc pi or t-stage filter. dielectric low-pass filter compo- nents, such as the lfl18924mtc1a052 (for operation in the 915 mhz and 868 mhz band) by murata manufacturing, co., ltd., represent an attractive alternative to discrete designs. an-917 describes how to replace the murata dielectric filter with an lc filter if desired. the immunity of the adf7020 to strong out-of-band interference can be improved by adding a band-pass filter in the rx path. apart from discrete designs, saw or dielectric filter components, such as the safch869mam0t00 or safch915mal0n00, both by murata, are well suited for this purpose. alternatively, the adf7020 blocking performance can be improved by selecting the high linearity mode, as described in table 5. internal rx/tx switch figure 33 shows the adf7020 in a configuration where the internal rx/tx switch is used with a combined lna/pa matching network. this is the configuration used in the adf7020-xdbx evaluation boards. for most applications, the slight performance degradation of 1 db to 2 db caused by the internal rx/tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. the design of the combined matching network must compensate for the reactance presented by the networks in the tx and the rx paths, taking the state of the rx/tx switch into consideration. 05351-033 pa lna pa_out rfin rfinb v bat l1 adf7020 optional bpf or lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin a ntenna figure 33. adf7020 with internal rx/tx switch
adf7020 dat a sheet rev. d | page 26 of 48 the procedure typically requires several iterations until an acceptable compromise is reached. the successful implementation of a combined lna/pa matching network for the adf7020 is critically dependent on the availability of an accura te electrical model for the pc board. in this context, the use of a suitable cad package is strongly recommended. to avoid this effort, however, a small form - factor reference design for the adf7020 is provided, including matching and harmonic filter compon ents . gerber files and schematics are available at www.analog.com . image r ejection c alibration the image channel in the adf7020 is 400 khz below the desired signal. the polyphase filter rejects this image with an asymm etric frequency response. the image rejection performance of the receiver is dependent on how well matched the i and q signals are in amplitude, and how well matched the quadrature is between them (that is, how close to 90o apart they are.) the uncalibrate d image rejection performance is approximately 30 db. however , it is possible to improve this performance by as much as 20 db by finding the optimum i/q gain and phase adjust settings. calibration procedure and setup the image rejection calibration works b y connecting an external rf signal to the rf input port. the external rf signal should be set at the image frequency and the filter rejection measured by mon itoring the digital rssi readback . as the image rejection is improved by adjusting the i /q gain an d phase , the rssi reading reduce s. the magnitude of the phase adjust is set by using the ir_phase_ adjust bits (r10_db[24:27 ]). this correction can be applied to either the i channel or q channel, by toggling bit (r 10_db28 ). the magnitude of the i/q gain is adjusted by the ir_gain_ adjust bits ( r10_db[16:20 ]). this correction can be applied to either the i or q channel using b it ( r10_db22 ), while the gain/attenuate bit (r10_db2 1) sets whether the gain adjustment defines a gain or attenuation adjust. the c alibration results are valid over changes in the adf7020 supply voltage. however, there is some variation with temperature . a typical plot of variation in image rejection over temperature after initial calibrations at + 25c, ?40c, and +85c is shown in figure 35. the internal t emperature sensor on the adf7020 can be used to determine if a new ir calibration is required. 05351-059 externa l signa l source rfin rfinb ma tching adf7020 ln a 4 4 phase adjustment q i from lo gain adjust pol yphase if fi l ter seria l inter f ace phase adjust register 10 rssi readback gain adjust register 10 rssi/ log am p 7-bit adc i/q gain/phase adjust and rssi measurement algorithm microcontroller figure 34 . image rejection calibration using the internal calibration source and a microcontroller
data sheet adf7020 rev. d | page 27 of 48 0 10 20 30 40 50 60 ?60 ?40 ?20 0 20 40 60 80 100 v dd = 3.0v if bw = 25khz wanted signal: rf freq = 430mhz modulation = 2fsk data rate = 9.6kbps, prbs9 f dev = 4khz level= ?100dbm interferer signal: rf freq = 429.8mhz modulation = 2fsk data rate = 9.6kbps, prbs11 f dev = 4khz 05351-058 temperature ( c) image rejection (db) cal at +25c cal at +85c cal at ?40c figure 35 . image rejection variation with temperature after initial calibrations at +25c, ?40c, and +85c transmit protocol an d coding considerations 05351-034 preamble sync word id field data field crc figure 36 . typical format of a transmit protocol a dc - free preamble pattern is recommended for fsk/ gfsk/ ask/ook demodulation. the recommend ed preamble pattern is a dc - balanced patt ern such as a 10101010 sequence . preamble patterns with longer run - length constraints such as 11001100 can also be used. however, t his results in a longer synchro nization time of the received bit stream i n the receiver. the remaining fields that follow the preamble header do not have to use dc - free coding. for these fields, the adf7020 can accommodate coding schemes with a run - length of up to several bytes with out any performance degradation, for example several bytes of 0x00 or 0xff. to help minimize bit errors when receiving these long runs of continuous 0s or 1s , it is important to choose a data rate and xtal combination that minimizes th e error between the actual data rate and the on - board cdr_clk/32. for example , if a 9.6 kbps data rate is desired, then using a n 11.0592 mhz xtal give s a 0% nominal error between the desired data rate and cdr_clk/32. an - 915 gives more details on supporting lon g run lengths on the adf7020. the adf7020 can also support manchester - encoded data for the entire protocol. manchester decoding needs to be done on the companion microcontroller , however. in this case, the adf7020 should be set up at the manchester chip or baud rate, wh ich is twice the effective data rate. devic e programming after initial power - up table 10 lists the minimum number of writes needed to set up the adf7020 in either tx or rx mode after ce is brought high. additional registers can also be written to tailor the part to a parti cular application, such as setting up sync byte detection or enabling afc. when going from tx to rx or vice versa, the user needs to write only to the n register to alter the lo by 200 khz and to toggle the tx/rx bit. table 10 . min imum register writes required for tx/rx setup mode register tx reg. 0 reg. 1 reg. 2 rx (ook) reg. 0 reg. 1 reg. 3 reg. 4 reg. 6 rx (g/fsk) reg. 0 reg. 1 reg. 3 reg. 4 reg. 6 tx ? rx reg. 0 figure 39 and figure 40 show the recommended programming sequence and associated timing for power - up from standby mode. interfacing to micro controller/dsp low level device drivers are availa ble for interfacing the adf7020 to the analog devices aduc84x analog microcontrollers, or the black fin ? adsp - bf53x dsps, using the hardware connections show n in figure 37 and figure 38. miso aduc84x adf7020 mosi sclock ss p3.7 p3.2/int0 p2.4 p2.5 data i/o data clk ce int/lock sread sle p2.6 p2.7 sdata sclk gpio 05351-035 figure 37 . aduc84x to adf7020 connection diagram mosi adsp-bf533 adf7020 miso pf5 rsclk1 dt1pri dr1pri rfs1 pf6 sdata sle data i/o int/lock ce v ddext gnd vdd gnd sck sclk sread data clk 05351-036 figure 38 . adsp - bf533 to adf7020 connection diagram
adf7020 data sheet rev. d | page 28 of 48 power consumption and battery lifetime calculations average power consumption can be calculated using average power consumption = (t on i avg_on + t off i powerdown )/( t on + t off ) using a sequenced power-on routine like that illustrated in figure 39 can reduce the i avg_on current and, hence, reduce the overall power consumption. when used in conjunction with a large duty-cycle or large t off , this can result in significantly increased battery life. analog devices, inc.s free design tool, adi srd design studio , can assist in these calculations. 2.0ma 3.65ma 14ma a d f 7 0 2 0 i d d time reg. ready t 1 wr0 t 2 wr1 t 3 vco t 4 wr3 t 5 wr4 t 6 wr6 t 7 19ma to 22ma agc/ rssi t 8 cdr t 9 afc t 10 rx data t 11 t off t on xtal t 0 0 5351-037 figure 39. rx programming sequence and timing diagram table 11. power-up sequence description parameter value description signal to monitor t 0 2 ms crystal starts power-up after ce is br ought high. this typically depends on the crystal type and the load capacitance specified. clkout pin t 1 10 s time for regulator to power up. the serial interface can be written to after this time. muxout pin t 2 , t 3 , t 5 , t 6 , t 7 32 1/spi_clk time to write to a single register. maximum spi_clk is 25 mhz. t 4 1 ms the vco can power-up in parallel with the crystal. this depends on the cvco capacitance value used. a value of 22 nf is recommended as a trade-off between phase noise performance and power-up time. cvco pin t 8 150 s this depends on the number of gain changes the agc loop needs to cycle through and agc settings programmed. th is is described in more detail in the agc information and timing section. analog rssi on test_a pin (available by writing 0x3800 000c) t 9 5 bit_period this is the time for the clock and data recovery circuit to settle. this typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. t 10 48 bit_period this is the time for the automatic frequency control circuit to settle. this typically requires 48-bit transitions to acquire lock and is usually covered by an appropriate length preamble. t 11 packet length number of bits in payload by the bit period.
data sheet adf7020 rev. d | page 29 of 48 2.0ma 3.65ma 14ma a d f 7 0 2 0 i d d time reg. ready t 1 wr0 t 2 wr1 t 3 xtal + vco t 4 wr2 t 5 15ma to 30ma txdata t 12 t off t on 05351-038 figure 40. tx programming sequence and timing diagram
adf7020 data sheet rev. d | page 30 of 48 adf7020 top view (not to scale) pin 1 indicator 13 14 15 16 17 18 19 20 21 22 23 24 cvco gnd1 gnd vco gnd gnd vdd cpout creg3 vdd3 osc1 osc2 muxout 48 47 46 45 44 43 42 41 40 39 38 37 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce creg1 vdd1 rfout rfgnd vdd rfin rfinb r lna rset vdd4 creg4 gnd4 35 vcoin 36 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 clkout data clk data i/o int/lock vdd2 creg2 adcin gnd2 sclk sread sdata sle 05351-056 vdd vdd chip enable to microcontroller to microcontroller configuration interface to microcontroller tx/rx signal interface rset resistor rlna resistor matching t-stage lc filter a ntenna c onnection vdd cvco cap vdd reference xtal loop filter figure 41. application circuit
data sheet adf7020 rev. d | page 31 of 48 serial interface the serial interface allows the user to program the fourteen 32- bit registers using a 3 - wire interface (sclk, sdata, a nd sle). signals should be cmos compatible. the serial interface is powered by the regulator and, therefore, is inactive when ce is low. data is clocked into the re gister, msb first, on the rising edge of each clock (sclk). data is transferred to one of fourteen latches on the rising edge of sle. the destination latch is determined by the value of the four control bits (c4 to c1). these are the bottom four lsbs, db3 to db0, as shown in the timing diagram in figure 3 . readback format the readback operation is initiated by writing a valid control word to the readback re gister and setting the readback enable bit (r7_db8 = 1). the readback can begin after the control word has been latched with the sle signal. sle must be kept high while the data is being read out. each active edge at the sclk pin clocks the readback word out successively at the sread pin (see figure 42), starting with the msb first. the data appearing at the first clock cycle following the latch operation must be ignored. the last (eighteenth) sclk edge puts the sread pin back in three - state. afc readback the afc readback is valid only during the receptio n of fsk signals with either the linear or correlator demodulator active. the afc readback value is formatted as a signed 16 - bit integer comprising bit rv1 to bit rv16 and is scaled according to the following formula: freq_rb [hz] = ( afc_readback demod_ clk )/ 2 15 in the absence of frequency errors, the freq_rb value is equal to the if frequency of 200 khz. note that, for the afc readback to yield a valid result, the down - converted input signal must not fall outside the bandwidth of the analog if filter. at low input signal levels, the variation in the readback value can be improved by averaging. rssi readback the rssi readback operation yields valid results in rx mode with ask or fsk signals. the format of the readback word is shown in figure 42 . it comprises the rssi level information (bit rv1 to bit rv7), the current filter gain (fg1, fg2), and the current lna gain (lg1, lg2) setting. the filter and lna gain are coded in accordance with the definitions in register 9. with the rec eption of ask modulated signals, averaging of the measured rssi values improves accuracy. the input power can be calculated from the rssi readback value as outlined in the rssi/agc section . battery voltage/ adcin/temperature sensor readback these three adc readback values are valid by just enabling the adc in register 8 without writing to the other registers. the battery voltage is measured at pin vdd4. the readback information is contained in bit rv1 to bit rv7. this also applies fo r the readback of the voltage at the adcin pin and the temperature sensor. from the readback information, the battery, adcin voltage or temperature can be obtained using v bat tery = ( battery_voltage_readback )/21.1 v adcin = ( adcin_voltage_readback )/42.1 temp erature = ? 40 c + (68.4 ? temperature_sensor_readback ) 9.32 silicon revision readback the silicon revision word is coded with four quartets in bcd format. the product code (pc) is coded with three quartets extending from bit rv5 to bit rv16. the revision code (rv) is coded with one quartet extending from bit rv1 to bit rv4. the product code for the adf7020 should read back as pc = 0x200. the current revision code should read as rv = 0x8. filter calibration readback the filter calibration readback word is contained in bit rv1 to bit rv8 and is for diagnostic purposes only. using the automatic filter calibration function, accessible through register 6, is recommended. before filter calibration is initiated, decimal 32 should be read back a s the default value. 05351-039 readback mode afc readback db15 rv16 x x rv16 0 rssi readback battery voltage/adcin/ temp. sensor readback silicon revision filter cal readback readback value db14 rv15 x x rv15 0 db13 rv14 x x rv14 0 db12 rv13 x x rv13 0 db11 rv12 x x rv12 0 db10 rv11 lg2 x rv11 0 db9 rv10 lg1 x rv10 0 db8 rv9 fg2 x rv9 0 db7 rv8 fg1 x rv8 rv8 db6 rv7 rv7 rv7 rv7 rv7 db5 rv6 rv6 rv6 rv6 rv6 db4 rv5 rv5 rv5 rv5 rv5 db3 rv4 rv4 rv4 rv4 rv4 db2 rv3 rv3 rv3 rv3 rv3 db1 rv2 rv2 rv2 rv2 rv2 db0 rv1 rv1 rv1 rv1 rv1 figu re 42 . readback value table
adf7020 dat a sheet rev. d | page 32 of 48 registers register 0 n register tr1 transmit/ receive 0 transmit receive 1 m3 m2 m1 muxout 0 regulator ready (default) 0 r divider output 0 n divider output 0 digital lock detect 1 analog lock detect 1 three-state 1 pll test modes 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - test modes ple1 pll enable 0 pll off 1 pll on 05351-040 n8 n7 n6 n5 n4 n3 n2 n1 n counter divide ratio 0 31 0 32 . . . 1 253 1 254 1 0 0 . . . 1 1 1 0 1 . . . . . . 1 1 1 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 0 1 1 . . . . . . 1 0 1 0 1 255 15-bit fractional-n 8-bit integer-n tx/rx pll enable muxout address bits n5 n4 n8 m5 m6 m7 m8 m12 m13 m15 n1 n2 n3 m14 m9 m10 m11 m4 m3 tr1 ple1 m1 m3 m2 c2(0) c1(0) c3(0) c4(0) m1 m2 n7 n6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 fractional divide ratio 0 1 2 . . . 32,764 32,765 32,766 32,767 m15 0 0 0 . . . 1 1 1 1 m14 0 0 0 . . . 1 1 1 1 m13 0 0 0 . . . 1 1 1 1 . . . . . . . . . . . m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 figure 43 . register 0 n register register 0 n register comments ? the tx/rx bit (r0_db27) configures the part in tx or rx mode and controls the s tate of the internal tx/rx switch. ? ) 2 _ _ ( 15 n fractional n integer r xtal f out + = ? if operating in 433 mhz band, with the vco band bit set, the desired frequency, f out , should be programmed to be twice the desired operating frequency, due to removal of the divide - by - 2 stage in th e feedback path.
data sheet adf7020 rev. d | page 33 of 48 register 1 oscillator/filter re gister r3 r2 r1 rf r counter divide ratio 0 0 . . . 1 1 2 . . . 7 1 0 . . . 1 0 1 . . . 1 x1 xtal osc 0 off 1 on va2 va1 frequency of operation 0 850 to 920 0 860 to 930 1 870 to 940 1 0 1 0 1 880 to 950 d1 xtal doubler 0 disable enabled 1 v1 vco band (mhz) 0 862 to 956 1 431 to 478 cp2 cp1 i cp (ma) 0 0 0.3 0 1 0.9 1 0 1.5 1 1 2.1 vb4 vb3 vb2 vb1 vco bias current 0 0.375ma 0 0.625ma . 1 1 0 . 1 0 1 . 1 0 0 0.125ma 0 0 0 0 . 1 3.875ma ir2 ir1 filter bandwidth 0 100khz 0 150khz 1 200khz 1 0 1 0 1 not used cl4 cl3 cl2 cl1 clkout divide ratio 0 off 0 0 . . . 1 0 1 0 . . . 1 2 4 . . . 0 0 1 . . . 1 0 0 0 . . . 1 30 vco bias cp current vco band xosc enable clockout divide address bits r counter xtal doubler vco adjust if filter bw ir2 ir1 cl1 cl2 cl3 cl4 cp2 vb1 vb3 vb4 va1 va2 vb2 x1 v1 cp1 d1 r3 c2(0) c1(1) c3(0) c4(0) r1 r2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db1 db0 db2 db3 05351-041 figure 44 . register 1 oscillator/filter register register 1 oscillator/filter register comments ? the vco adjust bits r1_db[20:21] should be set to 0 for operation in the 86 2 mhz to 870 mhz band and set to 3 for operation in the 902 mhz to 928 mhz band. ? the vco bias setting should be 0xa for operation in the 862 mhz to 870 mhz and 902 mhz to 928 mhz band s . all vco gain numbers are specified for these vco adjust and bias sett ings.
adf7020 dat a sheet rev. d | page 34 of 48 register 2 transmit modulation register (ask/ook mo de) p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output high level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm d6 x 0 0 0 0 . . 1 . . . . . . . . . d5 x x 0 0 . . . 1 d2 x x 0 0 1 . . 1 d1 x x 0 1 0 . . 1 power amplifier output low level ook mode pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm di1 0 1 txdata txdata modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5a 7a 9a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 05351-042 d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2(1) c1(0) c3(0) c4(0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 figure 45 . register 2 transmit modulation register (ask/ook mode) register 2 transmit modulation register (ask/ook mode) comments ? see the trans mitter section for a description of how the pa bias affects the power amplifier level. the default level is 9 a. if maximum power is needed, program this value to 11 a. ? see figure 13. ? d7, d8, and d9 are dont care bits.
data sheet adf7020 rev. d | page 35 of 48 regi ster 2 transmit modulation register (fsk mode) modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2(1) c1(0) c3(0) c4(0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 di1 0 1 txdata txdata pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5a 7a 9a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x d9 0 0 0 0 . 1 d3 0 0 0 0 . 1 . . . . . . . d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 for fsk mode, f deviation pll mode 1 f step 2 f step 3 f step . 511 f step p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 05351-043 figure 46 . register 2 transmit modulation register (fsk mode) register 2 transmit modulation register (fsk mode) comments ? f step = pfd /2 14 . ? when operating in the 431 mhz to 478 mhz band, f step = pfd /2 15 . ? pa bias default = 9 a.
adf7020 dat a sheet rev. d | page 36 of 48 register 2 transmit modulation register (gfsk/gook mode) modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2(1) c1(0) c3(0) c4(0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 di1 0 1 txdata txdata pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5a 7a 9a 11 a ic2 0 0 1 1 ic1 0 1 0 1 index_counter 16 32 64 128 d9 0 0 1 1 d8 0 1 0 1 gaussian ? ook mode normal mode output buffer on bleed current on bleed/buffer on 05351-044 mc3 0 0 . 1 mc2 0 0 . 1 gfsk_mod_control 0 1 . 7 mc1 0 1 . 1 d7 0 0 0 0 . 1 d3 0 0 0 0 . 1 . . . . . . . d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 divider_factor invalid 1 2 3 . 127 pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm figure 47 . register 2 transmit modulation register (gfsk/gook mode) register 2 transmit modulation register (gfsk/gook mode ) comments ? gfsk_deviation = (2 gfsk_mod_control pfd )/2 12 . ? when operating in the 431 mhz to 478 mhz band, gfsk_deviation = (2 gfsk_mod_control pfd)/2 13 . ? data rate = pfd /( index_counter divider_factor ). ? pa bias default = 9 a.
data sheet adf7020 rev. d | page 37 of 48 register 3 receiver clock register fs8 0 0 . 1 1 fs7 0 0 . 1 1 fs3 0 0 . 1 1 . . . . . . fs2 0 1 . 1 1 fs1 1 0 . 0 1 cdr_clk_divide 1 2 . 254 255 bk2 0 0 1 bk1 0 1 x bbos_clk_divide 4 8 16 sk8 0 0 . 1 1 sk7 0 0 . 1 1 sk3 0 0 . 1 1 . . . . . . sk2 0 1 . 1 1 sk1 1 0 . 0 1 seq_clk_divide 1 2 . 254 255 ok2 0 0 1 1 ok1 0 1 0 1 demod_clk_divide 4 1 2 3 sequencer clock divide cdr clock divide bb offset clock divide demod clock divide address bits sk8 sk7 fs1 fs2 fs3 fs4 fs8 sk1 sk3 sk4 sk5 sk6 sk2 fs5 fs6 fs7 ok2 ok1 c2(1) c1(1) c3(0) c4(0) bk1 bk2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db1 db0 db2 db3 05351-045 figure 48 . register 3 receiver clock register register 3 receiver clock register comments ? baseband offset clock frequency (bbos_clk) must be greater than 1 mhz and less th an 2 mhz, where divide clk bbos xtal clk bbos _ _ _ = ? the dem odulator clock (demod_clk) must be <12 mhz for fsk and < 6 mhz for ask, where divide clk demod xtal clk demod _ _ _ = ? data/clock recovery frequency (cdr_clk) should be withi n 2% of (32 data rate), where divide clk cdr clk demod clk cdr _ _ _ _ = note that this can affect your choice of xta l, depending on the desired data rate. ? the sequencer clock (seq_clk) supplies the clock to the digital receive block. it should be close to 100 khz for f sk and close to 40 khz for ask. divide clk seq xtal clk seq _ _ _ =
adf7020 dat a sheet rev. d | page 38 of 48 register 4 demodulator setup re gister demodulator lock setting postdemodulator bw demod select demod lock/ sync word match address bits dl8 dl7 dw3 dw4 dw5 dw6 dw10 dl1 dl3 dl4 dl5 dl6 dl2 dw7 dw8 dw9 dw2 dw1 c2(0) c1(0) c3(1) c4(0) ds1 ds2 lm2 lm1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db25 db1 db0 db2 db3 ds2 0 0 1 1 ds1 0 1 0 1 demodulator type linear demodulator correlator/demodulator ask/ook invalid lm2 0 0 0 0 1 1 demod mode 0 1 2 3 4 5 lm1 0 0 1 1 0 1 demod lock/sync word match serial port control ? free running serial port control ? lock threshold sync word detect ? free running sync word detect ? lock threshold interrupt/lock pin locks threshold demod locked after dl8?dl1 bits int/lock pin ? ? output output input ? dl8 0 1 0 1 x dl8 dl7 0 0 0 . 1 1 dl8 0 0 0 . 1 1 dl3 0 0 0 . 1 1 . . . . . . dl2 0 0 1 . 1 1 dl1 0 1 0 . 0 1 lock_threshold_timeout 0 1 2 . 254 255 05351-046 mode5 only figure 49 . register 4 demodulator setup register register 4 demodulator setup register comments ? demodulator mode 1, demodulator mode 3, demodulator mode 4, and demodulator mode 5 are modes that can be activated to allow the adf7020 to dem odulate data - encoding schemes that have run - length constraints greater than 7, when using the linear demodulator. ? post d emod_bw = demod_clk f cutoff 2 11 where the cutoff frequency ( f cutoff ) of the postdemodulator filter should typically be 0.75 times the d ata rate. ? for mode 5, timeout delay to lock threshold = ( lock_threshold_setting )/ seq_clk where seq_clk is defined in the register 3 receiver clock register section.
data sheet adf7020 rev. d | page 39 of 48 register 5 sync byte register pl2 0 0 1 1 pl1 0 1 0 1 sync byte length 12 bits 16 bits 20 bits 24 bits mt2 0 0 1 1 mt1 0 1 0 1 matching tolerance 0 errors 1 error 2 errors 3 errors sync byte sequence control bits sync byte length matching tolerance mt2 mt1 c2(0) c1(1) c3(1) c4(0) pl1 pl2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 05351-047 figure 50 . register 5 sync byte register register 5 sync byte register comments ? sync byte detect is enabled by programming bits r4_db[25:23] to 010 or 011. ? this register allows a 24 - bit sync byte sequence to be stored internally. if the sync byte detect mode is se lected, then the int/lock pin goes high when the sync byte is detected in rx mode. once the sync word detect signal goes high, it goes low again after nine data bits. ? the transmitter must transmit the msb of the sync byte first and the lsb last to ensure p roper alignment in the receiver sync byte detection hardware. ? choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456.
adf7020 dat a sheet rev. d | page 40 of 48 register 6 correlator/demodulat or register discriminator bw if filter divider lna current lna mode dot product rxdata invert if filter cal mixer linearity rx reset address bits fc4 fc3 fc7 td5 td6 td7 td8 lg1 li1 ml1 ca1 fc1 fc2 li2 td9 td10 dp1 td4 td3 fc8 fc9 ri1 c2(1) c1(0) c3(1) c4(0) td1 td2 fc6 fc5 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ri1 0 1 rxdata invert rxdata rxdata ca1 0 1 filter cal no cal calibrate 0 1 rxreset normal opperation demod reset 0 1 rxreset normal opperation cdr reset ml1 0 1 mixer linearity default high dp1 0 1 dot product cross product dot product lg1 0 1 lna mode default reduced gain fc3 0 0 . . . . 1 fc1 1 0 . . . . 1 filter clock divide ratio 1 2 . . . . 511 fc2 0 1 . . . . 1 fc9 0 0 . . . . 1 fc6 0 0 . . . . 1 . . . . . . . . fc5 0 0 . . . . 1 fc4 0 0 . . . . 1 li2 0 li1 0 lna bias 80 0 a (default) 05351-048 figure 51 . register 6 correlator /demodulator register register 6 correlator/demodulator register comments ? see the fsk correlator/demodulator section for an example of how to determine register settings. ? nonadherence to correlator programming guidelines results i n poorer sensitivity. ? the filter clock is used to calibrate the if filter. the filter clock divide ratio should be adjusted so that the frequency i s 50 khz. the formula is xtal/filter_clock_divide. ? the filter should be calibrated only when the crystal osc illator is settled. the filter calibration is initiated every time bit r6_db19 is set high. ? discriminator_bw = ( demod_clk k )/(800 10 3 ). see the fsk correlator/demodulator section. maximum value = 600. ? when lna mode = 1 (reduce d gain mode), the rx is prevented from selecting the highest lna gain setting. this can be used when linearity is a concern. see table 5 for details of the different rx modes.
data sheet adf7020 rev. d | page 41 of 48 register 7 readback setup regis ter ad1 ad2 rb1 rb2 rb3 db8 db7 db6 db5 db4 db3 db2 c2(1) c1(1) control bits db1 db0 c3(1) c4(0) readback select adc mode ad2 0 0 1 1 ad1 0 1 0 1 adc mode measure rssi battery voltage temp sensor to external pin rb2 0 0 1 1 rb1 0 1 0 1 readback mode afc word adc output filter cal silicon rev rb3 0 1 readback disabled enabled 05351-049 figure 52 . register 7 readback setup register register 7 readback setup register comments ? readback of the measured rssi value is valid only in rx mode. to enable readback of the battery voltage, the temperature sens or, or the voltage at the extern al pin in rx mode, agc function in register 9 must be disabled. to read back these parameters in tx mode, the adc must first be powered up using register 8 because this is off by default in tx mode to save powe r. this is the recommended method of using the battery readback function because most configurations typically require agc. ? readback of the afc word is valid in rx mode only if either the linear demodulator or the correlator/demodulator is active. ? see the readback format secti on for more information.
adf7020 dat a sheet rev. d | page 42 of 48 register 8 power - down test register pd1 pd2 pd3 pd4 pd5 db8 db7 db6 db5 db4 db3 db2 c2(0) c1(0) control bits db1 db0 c3(0) c4(1) log amp/ rssi synth enable vco enable lna/mixer enable filter enable adc enable demod enable internal tx/rx switch enable pa enable rx mode pd7 db13 db12 db11 lr1 pd6 db10 db9 lr2 sw1 pd7 0 1 pa (rx mode) pa off pa on sw1 0 1 tx/rx switch default (on) off pd6 0 1 demod enable demod off demod on pd5 0 1 adc enable adc off adc on lr2 x x lr1 0 1 rssi mode rssi off rssi on pd4 0 1 filter enable filter off filter on pd3 0 1 lna/mixer enable lna/mixer off lna/mixer on ple1 (from reg 0) 0 0 0 0 1 pd2 0 0 1 1 x loop condition vco/pll off pll on vco on pll/vco on pll/vco on pd1 0 1 0 1 x 05351-050 figure 53 . register 8 power- down test register register 8 power - down test register comments ? for a combined lna/pa matching network, bit r8_db12 should always be set t o 0. this is the power - up default condition. ? it is not necessary to write to this register under normal operating conditions.
data sheet adf7020 rev. d | page 43 of 48 register 9 agc register agc high threshold lna gain filter gain digital test iq agc search gain control filter current agc low threshold address bits fg2 fg1 gl5 gl6 gl7 gh1 gh5 gh6 gs1 gc1 lg1 lg2 gh7 gh2 gh3 gh4 gl4 gl3 c2(0) c1(1) c3(0) c4(1) gl1 gl2 fi1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db25 db1 db0 db2 db3 fi1 0 1 filter current low high gs1 0 1 agc search auto agc hold setting gc1 0 1 gain control auto user fg2 0 0 1 1 fg1 0 1 0 1 filter gain 8 24 72 invalid lg2 0 0 1 1 lg1 0 1 0 1 lna gain <1 3 10 30 gl3 0 0 0 1 . . . 1 1 0 gl1 1 0 1 0 . . . 0 1 0 agc low threshold 1 2 3 4 . . . 78 79 80 gl2 0 1 1 0 . . . 1 1 0 gl7 0 0 0 0 . . . 1 1 1 gl6 0 0 0 0 . . . 0 0 0 gl5 0 0 0 0 . . . 0 0 1 gl4 0 0 0 0 . . . 1 1 0 gh3 0 0 0 1 . . . 1 1 0 gh1 1 0 1 0 . . . 0 1 0 agc high threshold 1 2 3 4 . . . 78 79 80 gh2 0 1 1 0 . . . 1 1 0 gh7 0 0 0 0 . . . 1 1 1 gh6 0 0 0 0 . . . 0 0 0 gh5 0 0 0 0 . . . 0 0 1 gh4 0 0 0 0 . . . 1 1 0 05351-051 figure 54 . register 9 agc register register 9 agc register comments ? this regi ster does not need to be programmed in normal operation. default agc_l ow _t hreshold = 30, default agc_h igh _t hreshold = 70. see the rssi/agc section for details. default register setting = 0xb2 31e9 . ? agc high and low settings must b e more than 30 apart to ensure correct operation. ? lna gain of 30 is available only if lna mode, r6_db15, is set to 0.
adf7020 dat a sheet rev. d | page 44 of 48 register 10 agc 2 register agc delay i/q gain adjust leak factor i/q phase adjust gain/attenuate reserved select i/q select i/q peak response address bits r1 siq1 ph3 gl4 gl5 gl6 gl7 dh4 gc1 gc3 gc4 gc5 ud1 gc2 dh1 dh2 dh3 pr4 pr3 ph4 siq2 c2(1) c1(0) c3(0) c4(1) pr1 pr2 ph2 ph1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 siq2 0 1 select iq phase to i channel phase to q channel siq2 0 1 select iq gain to i channel gain to q channel default = 0xa default = 0x2 default = 0xa 05351-052 if db21 = 0, then gain is selected. if db21 = 1, then attenuate is selected figure 55 . register 10 agc 2 register register 10 agc 2 register comments ? this reg ister is not used under normal operating conditions. ? for ask/ook modulation, the recommended settings for operation over the full input range are peak response = 2 , leak factor = 10 (default), and agc delay =10 (default). bit db31 to bit db16 should be cle ared. for bit - rates below 4kbps the agc_wait_time can be increased by setting the agc_delay to 15. the seq_clk should also be set at a minimum. register 11 afc register afc scaling coefficient control bits afc enable m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m16 ae1 m3 c2(1) c1(1) c3(0) c4(1) m1 m2 db16 db15 db14 db17 db20 db19 db18 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db1 db0 db2 db3 ae1 0 1 internal afc off on 05351-053 figure 56 . register 11 afc register register 11 afc regis ter comments ? see the internal afc section to program the afc scaling coefficient bits. ? the afc scaling coefficient bits can be programmed using the following formula: afc_scaling_coefficient = round ((500 2 24 )/ xtal )
data sheet adf7020 rev. d | page 45 of 48 register 12 test register counter reset digital test modes - test modes analog test mux manual filter cal osc test force ld high source prescaler pll test modes address bits sf6 sf5 t5 t6 t7 t8 sf1 sf2 sf3 sf4 t9 t4 t3 pre c2(0) c1(0) c3(1) c4(1) t1 t2 qt1 cs1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 p 0 1 prescaler 4/5 (default) 8/9 cr1 0 1 counter reset default reset cs1 0 1 cal source internal serial if bw cal default = 32. increase number to increase bw if user cal on 05351-054 cr1 figure 57 . register 12 test register register 12 test register comments this register does not need to be written to in normal operation. the default test mode is 0x0000 000c, which puts the part in normal operat ion. using the test dac on the adf7020 to implement analog fm d emodulation and measuring of snr the test dac allows the output of the postdemodulator filter for both the linear and correlator/demodulators ( see figure 30 and figure 31 ) to be viewed externally. it takes the 16 - bit filter output and converts it to a high frequency, single - bit output using a second - order - converter. the output can be viewed on the clkout pin. this signal, when filtered approp riately, can then be used to ? monitor the signals at the fsk/ask postdemodulator filter output. this allows the demodulator output snr to be measured. eye diagrams can also be constructed of the received bit stream to measure the received signal quality. ? pr ovide analog fm demodulation. while the correlators and filters are clocked by demod_clk, cdr_clk clocks the test dac. note that although the test dac functions in a regular user mode, the best performance is achieved when the cdr_clk is increased up to or above the frequency of demod_clk. the cdr block does not function when this condition exists. programming the test register, register 12, enables the test dac. in correlator mode, this can be done by writing to digital test mode 7 or 0x0001c00c. to v ie w the test dac output when using the linear demodu - lator, the user must remove a fixed offset term from the signal using register 13. this offset is nominally equal to the if frequency. the user can determine the value to program by using the frequency erro r readback to determine the actual if and then programming half this value into the offset removal field. it also has a signal gain term to allow the usage of the maximum dynamic range of the dac. setting up the test dac ? digital test modes = 7: enables the test dac, with no offset removal (0x0001 c00c). ? digital test modes = 10: enables the test dac, with offset removal (needed for linear demodulation only, 0x02 800c). the output of the active demodulator drives the dac, that is, if the fsk correlator/demodu lator is selected, the correlator filter output drives the dac. the evaluation boards for the adf7020 contain land patterns for placement of an rc filter on the clkout line. this is typically designed so that the cut - off frequency of the filter is above t he demodulated data rate.
adf7020 dat a sheet rev. d | page 46 of 48 register 13 offset removal and s ignal gain register kp ki control bits pulse extension test dac gain test dac offset removal pe1 pe2 pe3 pe4 c2(0) c1(1) c3(1) c4(1) db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 pe4 0 0 0 . . . 1 pe3 0 0 0 . . . 1 pe2 0 0 1 . . . 1 pulse extension normal pulse width 2 pulse width 3 pulse width . . . 16 pulse width pe1 0 1 0 . . . 1 05351-055 ki default = 3 kp default = 2 figure 58 . register 13 offset removal and signal gain register register 13 offset removal and signal gain register comments ? because the linear demodul ators output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. the offset can be removed, up to a maximum of 1.0 , and gained to use the full dynamic range of the dac: dac_input = (2 test_dac_gain ) ( sign al ? test_dac_offset_removal /4096) ? ki (default) = 3. kp (default) = 2 .
data sheet adf7020 rev. d | page 47 of 48 outline dimensions for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indicator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 4.25 4.10 sq 3.95 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 08-16-2010-b figure 59. 48-lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp-48-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option 2 ADF7020BCPZ ?40c to +85c 48-lead lead frame chip scale package [lfcsp_wq] cp-48-5 ADF7020BCPZ-rl ?40c to +85c 48-lead lead frame chip scale package [lfcsp_wq] cp-48-5 eval-adf70xxmbz control mother board eval-adf70xxmbz2 evaluation platform eval-adf7020dbz1 902 mhz to 928 mhz daughter board eval-adf7020dbz2 860 mhz to 870 mhz daughter board eval-adf7020dbz3 430 mhz to 445 mhz daughter board 1 z = rohs compliant part. 2 formerly cp-48-3 package.
adf7020 data sheet rev. d | page 48 of 48 notes ? 2005 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05351 - 0 - 8/12(d)

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